Overview
Our rapidly scaling client in Toronto is seeking an experienced ASIC Designer.  Our client develops innovative solutions based on their internal IP to address the latest and toughest challenges for SOC designs. In this role, you will have the ability to work in multiple disciplines including architecture, RTL, verification, or even backend P&R, and interact with sales, marketing, engineering, post silicon and customer success teams! 

Core Responsibilities

• Design engineering experience from RTL to GDS delivery
• Emphasis on RTL Design from specification to verification and sign-off
• Expert in Synthesis, Timing Closure, and design sign-off
• Ability to work with application engineers to support customer engagements
• Ability to work with silicon validation team for post-silicon analysis
• Complete ownership of IP functionality to final design Sign-off

Requirements

• Experienced SOC leader with 5+ years of experience
• Motivated, hands-on, independent and effective leader with team spirit
• Working knowledge of SOC designs, and experience with backend P&R closure
• Block-level and system-level Verilog verification in an ASIC environment
• Familiarity with Verilog, UVM, System Verilog and Python 
• Full-flow verification (RTL, gates, gates with SDF)
• Working knowledge of Block P&R, CTS, Extraction, Timing Closure, DRC / LVS
• Experience with multiple ASIC tapeout experience in different technology nodes

How to Apply?
All qualified and interested applicants can apply directly to Aaron Ravensbergen by sending an email with attached resume to Aaron.ravensbergen@talentlab.com. You may also apply directly on our website at www.talentlab.com. Although we thank all applicants for their interest, only those in consideration will be contacted.