Overview:

Our client is the world's leading developer of next-generation of always connected Edge-AI processing technology and is committed to building a world-class organization that will lead the industry. The ASIC Edge AI Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Audio/Edge AI subsystem across a broad range of mobile, XR, compute, and automotive products.

Responsibilities:

Owning end to end system architecture
Capturing detailed technology requirements working closely with product, hardware and software engineering teams
Developing detailed ASIC system architectures to support requirements and authoring subsystem hardware specifications
Defining architecture validation plans and reviewing development results
Optimization and debug via modelling, system simulation and testing across key criteria including power and performance.
Collaborating, reviewing and enabling design and system teams to execute on dependent specifications
Post-silicon commercialization support and customer engineering documentation
Defining and patenting novel architectures that drive industry leadership.
Oversees hardware architecture for ASIC systems development for a variety of products.
Determines architecture design, and validation via system simulation.
Defines module interfaces/formats for simulation.
Evaluates all aspects of the HW architecture flow from high-level development to validation and review.
Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results.
Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes.
Uses language such as HDL, C/C++, System C, Perl, Python.
Provides technical expertise for next generation initiatives.

Principal Duties and Responsibilities:

Leverages experience in DSP, machine learning algorithms, SoC hardware and computer architecture concepts to develop proposals to address system audio and edge-AI requirements using processor, memory, bus and low-power design techniques.
Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power.
Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met.
Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system.
Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems.
Writes technical documentation and provides technical expertise for design or project reviews and project meetings.
Acts as a tech lead on small to large projects and owns team deliverables of the project.

Preferred Qualifications:

Bachelor's/Master’s or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science.
Min 2+ years ASIC design, verification, or related work experience.
Min 2+ years experience with computer architecture and design tools.
Experience with bus design and/or cache, memory controllers, low power design
Min 2+ years experience with scripting tools and programming languages.
Min 2+ years experience with design verification methods.

How to Apply?
All qualified and interested applicants can apply directly to Aaron Ravensbergen by sending an email with attached resume to Aaron.ravensbergen@talentlab.com. You may also apply directly on our website at www.talentlab.com. Although we thank all applicants for their interest, only those in consideration will be contacted.

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