Overview:

We are partnered with a global leader in the semiconductor industry that is focused on development of connected devices and SoC. Our client is currently looking to expand their ASIC Design team, that is working on technology that will bring “Cognition” to all connected devices: That means devices that don’t just think, but instinctively react to their surroundings.

Currently they are looking for an experienced ASIC Design Engineer for a critical position within the team that will innovate and design leading edge AI/video processing hardware IP for for their DSP processors. 

Responsibilities: 

• Design high speed, low power digital hardware solutions using SystemVerilog
• Contribute to definition, micro-architecture and documentation of HW IP
• Collaborate closely with the Verification team to test, debug and close coverage on the design
• Write functional coverage and assertions using SystemVerilog
• Evaluate synthesis results to verify the design meets the speed, power and area targets
• Support internal hardware integration SW teams around the world
• Resolve architecture, design, or verification problems by applying sound ASIC engineering practices with minimal supervision
• Use of various design tools (VCS Simulator, Synopsys Compiler , Linting, CDC, LEC, CLP etc.) to check and improve design quality
• Provide ideas and further the innovation of ASICs, IP cores, and process flows

Requirements: 

• Bachelor's degree in Science, Engineering, or related field
• Minimum of 8+ years of ASIC design, verification, or related work experience.

How to Apply?
All qualified and interested applicants can apply directly to Aaron Ravensbergen by sending an email with attached resume to Aaron.ravensbergen@talentlab.com. You may also apply directly on our website at www.talentlab.com. Although we thank all applicants for their interest, only those in consideration will be contacted.