Overview: 
We are partnered with a global leader in the semiconductor industry. Our clients Low Power Machine Learning IP team is looking for experienced ASIC Design Verification Engineers for all levels.

Responsibilities:

• Define IP verification strategy
• Create verification environment using UVM/System Verilog
• Drive test plan development, execution and verification closure in conjunction with designers/architects and other verification team members
• Resolve architecture, design, or verification problems by applying sound ASIC engineering practices
• Lead complex activities through development cycle
• Provide technical supervision to others and have ability to lead by example
• Identify opportunities for productivity improvements. Drive and adopt new verification methodologies and flows for efficiency improvements

Requirements: 

• Thorough understanding of Digital design concepts
• Strong UVM, System Verilog skills
• General Machine Learning knowledge
• Understanding of Bus protocols like AHB/AXI
• Perl, python scripting experience
• Quick understanding of Specs and Standards and developing relevant and thorough test plans
• Strong communication skills and works well in a team environment

Minimum Requirements:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, or related work experience.

How to Apply?
All qualified and interested applicants can apply directly to Aaron Ravensbergen by sending an email with attached resume to Aaron.ravensbergen@talentlab.com. You may also apply directly on our website at www.talentlab.com. Although we thank all applicants for their interest, only those in consideration will be contacted.