logo

View all jobs

RTL Design Engineer (All Levels)

Ottawa, Ontario

Overview:
We are partnered with a growing AI-enhanced security processor company that is redefining the control and management of every digital system. Founded in 2017, the organization continues to rapidly grow, and they are building a new site from the ground up in Ottawa, ON. 

Responsibilities:

  • Help develop the design and implementation of SoCs;
  • Micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks;
  • Top-level and block-level performance, bandwidth, power, and cost analysis and optimization;
  • Work with FPGA engineers to perform early prototyping; and
  • Support test program development, chip validation, and chip life until production maturity.
  • Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.
Requirements: 
  • 2-10 years of experience in RTL logic design, verification, synthesis, and timing optimization;
  • Proficient in writing clear, implementable micro-architecture specifications;
  • Expertise in writing efficient RTL code in Verilog;
  • Good understanding of assertions, coverage analysis, synthesis, and timing closure;
  • Experience in revision control, regression and bug-tracking tools;
  • Fluency with scripting languages (e.g., Perl, Python);
  • Must have gone through at least one tapeout;
  • Preferred: Lab debug/bring-up experience
How to Apply?
All qualified and interested applicants can apply directly to Aaron Ravensbergen by sending an email with attached resume to Aaron.ravensbergen@talentlab.com. You may also apply directly on our website at www.talentlab.com. Although we thank all applicants for their interest, only those in consideration will be contacted.

More Openings

Analog IC Designer
Business Quality Analyst
System Engineer

Share This Job

Powered by