Our client is rapidly growing and looking to expand their Physical Design team in Ottawa. You will be working on the most advanced technology nodes (.3nm) with a chance to contribute work with the best!
You will be responsible for the following task;
Block level floorplan
Clock tree synthesis
Place & Route
STA, timing closure
IR/EM analysis and fix
DRC/LVS/ERC clean up
Tape-out sign off
- Bachelor or Master’s degree in Electrical Engineering or Computer Science.
- 3 plus years Netlist (or RTL)-GDS physical implementation experience
- In depth knowledge of major EDA tools/design flows
- Experience with TSMC N28 or below technology
- Experience in block level implementation or chip integration and signoff
- Experience in Perl/TCL language programming.
- Proven record in multi-million gate design production tapeouts
- Proven ability to analyze issues, solve problems and bring closure
Experience in any of the following is a plus:
- TSMC N16 and below technology
- Low-power implementation methodology
- Advanced timing sign-off methodology
- Able to independently complete Netlist-GDS P&R, sign-off task