Analog IC Layout Engineer
We have partnered with a leading player in the semiconductor industry that is looking to add an Analog IC Layout Engineer to their growing team. The successful candidate will perform custom layout implementing IC design in deep-submicron CMOS/FinFET. In addition, you will accomplish compact high performance memory and mixed signal layout: Memory, Mixed-Signal IP Blocks, I/O-PAD Ring, etc. using industry standard custom CAD tools, layout, DRC, LVS, RC Extraction etc.
- Hands-on working knowledge of CAD tools; expert user of at least one large CAD custom layout tool flow
- Ability to deliver high quality layouts independently
- Demonstrated knowledge writing scripts and software macros to enhance productivity as required
- Some experience with an APR (automated place and route) ASIC backend flow is advantageous
- Commitment to on-time delivery of top quality layouts
- Ability to learn and adapt to new processes and design styles or constraints
- A team player with good communication skills; excellent working knowledge of English (written and oral).
- Scripting in Cadence Skill, Pearl, Compiler-Tiler, Linux
- Verilog RTL ASIC design flow
- Knowledge of physical design and layout and automatic place and route tools
- Memory compiler layout design
- Standard cell library layout design
- High-speed Mixed-Signal, Analog or RF IC layout design
- Layout database verification
- Demonstrated experience in team leadership
- FinFET experience is an asset
How to apply?
All interested and qualified applicants should apply directly to our lead Recruiter Peter Mills at email@example.com
, or on our website at www.talentlab.com
. Although we thank all interested applicants, only those in consideration will be contacted.