If you are tired of feeling stuck in your "cube farm" then this start-up is for you!
Fresh of a new round of funding this group of proven industry experts is looking grow their Engineering team. You will be an early member of this team with an excellent chance to grow!
- Create and implement block, chip & system-level Design Verification Plan from ASIC concept to silicon
- Design / Implement simulation testbenches, reference models and bus-functional models, assertions / infrastructure in System Verilog, C/C++, SystemC and Python
- Work closely with rest of ASIC design,and SW teams to implement the SOC
- Implement/maintain verification infrastructures, tools, and flows
- 2+ years of design verification experience on complex ASIC’s
- Strong System Verilog, UVM and ASIC debugging skills on a variety of platforms and simulators (VCS)
- Strong C/C++ programming and scripting (e.g. Makefiles, Python, Perl, tcl) skills
- Ability to innovate, adapt and work independently and in a team in a fast-paced environment
- Experience with PCIe, Ethernet and high speed data communication products
All interested and qualified applicants should apply directly at www.talentlab.com.